This invention relates to test equipment for electronic components; and in particular, it relates to equipment for measuring the delay with which a digital signal propagates through an integrated circuit logic chip.
Each integrated circuit logic chip has at least one input terminal, at least one output terminal, and multiple logic gates which interconnect the input terminals to the output terminals. When a digital signal is applied to an input terminal, it propagates through the logic gates and generates an output signal on one or more output terminals. Often, the speed at which the signal propagates from an input terminal to an output terminal is extremely important. However, as logic gates become faster and faster in their operation, that propagation speed becomes more and more difficult to measure with a high degree of accuracy.
One example of an integrated circuit logic chip in which propagation speed is critical is a clock distribution chip. It receives a clock signal on an input terminal and replicates that clock signal on multiple output terminals. Such a chip is used in multichip computers to provide respective clock signals to multiple computer chips. Output terminal #1 of the clock distribution chip is coupled to a subset of computer chips #1A, #1B, . . . ; output terminal #2 of the clock distribution chip is coupled to another subset of computer chips #2A, #2B, . . . ; etc. The number of chips in each subset is typically limited to about eight. In such a multichip computer, the propagation delays from the input terminal of the clock distribution chip to that chips output terminals must be closely matched; otherwise, errors due to logic races will occur.
A logic race can be visualized by considering the case where the propagation delay from the input terminal to output terminal #1 of the clock distribution chip is very short in comparison to the propagation delay to output terminal #2. In that case, computer chip #1A will be clocked relatively early in comparison to computer chip #2A. When computer chip #1A is clocked, output signals from that chip will change. And, if some of those output signals are sent to computer chip #2A, those signals may change at the same time that the computer chip #2A receives its clock signal.
To avoid the above described logic race, it is desirable to be able to very accurately measure the propagation delay from the input terminal of the clock distribution chip to each of its output terminals. However, any such measurement will always have a certain accuracy error associated with it which depends on the instrument that is used to make the measurement. And if the propagation delay through the chip is so short that it approaches the accuracy of the delay measuring instrument, the problem which is then posed is how can the propagation delay even be measured.
Accordingly, a primary object of the invention is to provide an integrated circuit: logic chip tester in which the above described problem is overcome.